1. Field of the Invention
The present invention generally relates to a driving circuit built in an active matrix panel and, more particularly, to a data line driving circuit formed by a thin-film transistor (hereafter referred to as a TFT) based on polycrystalline silicon.
2. Description of Related Art
In an active matrix panel with TFTs made of polycrystalline silicon, a TFT is provided for each picture element electrode arranged in a matrix and data lines intersect scan lines at right angles. A data line driving circuit and a scan line driving circuit for respectively driving each of the data lines or each of the scan lines are built into the active matrix panel.
A known data line driving circuit is shown in FIG. 5. In FIG. 5, reference numeral 1 denotes a picture element section, in which a plurality of scan lines 11, 12, and so on and a plurality of data lines 21, 22, and so on are arranged in an orthogonal manner. TFTs 31, 32, etc. are formed near where the scan lines and the data lines intersect. The gate electrode of each TFT is connected to a corresponding scan line and the drain electrode of the TFT is connected to a corresponding data line. The source electrodes of the TFTs 31, 32, etc. are connected to respective picture element electrodes 41, 42, etc. arranged in a matrix. A liquid crystal (LC) is sandwiched between each of the picture element electrodes and its opposing electrode COM. Reference numerals 51, 52, etc. denote storage capacitors. Referring to FIG. 5, each of the picture element electrodes 41, 42, etc. is represented in the upper line of each LC. The opposing electrode COM is a common electrode and is represented by a terminal for convenience of description.
Each of the scan lines 11, 12, etc. is supplied with a scan line signal from a corresponding scan line driving circuit, not shown. The data lines 21, 22, etc. are inserted with respective sampling switches 61, 62, etc. which sample video data signals, and supply the sampled video signals to the data lines. Reference numeral 8 denotes a shift register for generating a sampling pulse for switching on the sampling switches 61, 62, etc. The outputs of the stages constituting the shift register 8 are sent to respective buffers 71, 72, etc. each comprising a plurality of inverters. The sampling pulses output from these buffers are input into the respective sampling switches 61, 62, etc.
The shift register 8 includes a latch circuit 81 that operates at a rising edge of a clock signal CLK and a latch circuit 82 that operates at a falling edge of the clock signal CLK, these latch circuits being alternately connected with each other. The input terminal of the first-stage latch circuit 81 is applied with a start signal STH that goes logic high level (hereafter referred to as HIGH) for about one period of the clock signal CLK. The clock signal CLK determines the timing in which data is written to the LC of each picture element and is in synchronization with a dot clock.
In more detail, the latch circuit 81 is composed of a clocked inverter 811 to which an input signal is applied, an inverter 812 to which output of the clocked driver 811 is applied, and a clocked inverter 813 arranged between the output and input of the inverter 812. The clocked inverter 813 is arranged in the direction inverse to the inverter 812. The clocked inverter 811 is on when the clock signal CLK is HIGH. The clocked inverter 813 is on when the clock signal CLK is at logic low level (hereafter referred to as LOW). The latch circuit 82 is generally of the same in constitution as the latch circuit 81, but the clocked inverter 821 is on when the clock signal CLK is LOW and the clocked inverter 823 is on when the clock signal CLK is HIGH. Thus, in the latch circuit 82, the timing in which the clocked inverters go on is reverse to that of the latch circuit 81. The shift register 8, the buffers 71, 72, etc. and the sampling switches 61, 62, etc. together constitute a data line driving circuit 9.
FIG. 6 shows a timing chart indicative of operations of the above-mentioned related-art data line driving circuit. When a start signal STH is input in the above-described known circuit, a sampling pulse A1, which is the output of the first-stage latch circuit 81 of the shift register 8 rises, with a slight delay, along with the rising of the clock signal CLK, and goes HIGH for one period of the clock signal CLK. Next, the sampling pulse A1 passes the buffer 71 to be delayed further, becoming a sampling pulse B1, which goes HIGH for one period of the clock signal CLK. Then, the delayed sampling pulse B1 is applied to the gate of the TFT constituting the sampling switch 61. While the sampling pulse B1 is HIGH, a video signal is supplied to the data line 21. Likewise, after the next falling of the clock pulse CLK, a sampling pulse A2 is output with a delay from the next-stage latch circuit 82 of the shift register 8. The sampling pulse A2 passes the buffer 72 to be further delayed, causing a sampling pulse B2 to go HIGH. The sampling pulse B2 supplies the video signal to the data line 22 through the sampling switch 62.
In the above-described constitution, each sampling switch is constituted by one TFT. An analog sampling switch comprised of two TFTs is also used often, an example of which is illustrated in FIG. 7. Referring to FIG. 7, each sampling switch 91, 92, etc. comprises an analog switch based on a p-channel TFT and an n-channel TFT. Buffers 101, 102, etc. differ in constitution from the buffers 71, 72, etc. shown in FIG. 5. A data line driving circuit 9 comprises a shift register 8, the buffers 101, 102, etc., and the sampling switches 91, 92, etc.
In the constitution of FIG. 7, signals having opposite polarities must be applied to the gate electrodes of the two TFTs, which inevitably increases the number of inverters for each buffer and more inverters for matching the two TFTs in on and off timing. Therefore, as shown in FIG. 8, these inverters considerably delay the signals within the buffers 101, 102, etc. These delayed sampling pulses B1 and C1, B2 and C2, etc. turn on/off the respective sampling switches 91, 92, etc.
In the known art shown in FIGS. 5 and 7, many inverters in the buffers considerably delay the sampling pulses to be output from the shift register. In addition, the shift register itself has many inverters, further increasing the delay. The cumulative delay disables the turning on/off of the sampling switches with the originally intended timing for writing a video signal to liquid crystal picture elements. This result in a nonuniformity of display and degrades display quality. Large variations in TFT characteristics lead to an accompanying large variation in the delay amount and further degrade display quality.
In addition, in the examples, the HIGH level periods of sampling pulses partially overlap each other between adjacent picture elements. In the overlapped portion, the adjacent sampling switches turn on together. Consequently, in this overlapped portion, two or more data lines are connected to the video signal line, increasing the resistance and parasitic capacity of the video signal line, thereby making the video signal less sharp. This also adds to the degradation of display quality.